Physical layer circuit, data transfer control device, and electronic instrument

ABSTRACT

A physical layer circuit including: a VBUS detection circuit which makes a VBUS detection signal VBDET active when a VBUS voltage has exceeded a predetermined voltage; a receiver circuit which performs reception processing using signals DP and DM; and a reception control circuit which outputs an enable signal to the receiver circuit. When the signal VBDET is inactive, the reception control circuit makes the enable signals COMPENB, SEENB 1  and SEENB 2  inactive and disables the receiver circuit. When signals FCOMPENB, FSEENB 1  and FSEENB 2  set by a processing section are active but the signal VBDET is inactive, the reception control circuit makes the signals COMPENB, SEENB 1  and SEENB 2  inactive.

Japanese Patent Application No. 2003-421082, filed on Dec. 18, 2003, ishereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a physical layer circuit, a datatransfer control device, and an electronic instrument.

In recent years, Universal Serial Bus (USB) has attracted attention asan interface standard for connecting electronic instruments. USB iswidely used as an interface for connecting a personal computer as a hostwith a printer or an optical disk drive as a device (peripheral).

In recent years, it has been demanded that a portable telephone or thelike be provided with a data transfer control device which implementsUSB. In the case of incorporating a USB data transfer control deviceinto a portable telephone which operates using a battery, it ispreferable to reduce power consumption of the data transfer controldevice to be incorporated. Various conventional technologies have beenproposed as a technology for implementing a reduction of powerconsumption.

In USB, a data transfer operation is started after a USB cable isconnected and the voltage of a VBUS line rises. Therefore, if electricpower is consumed by a receiver circuit of the data transfer controldevice before the USB cable is connected, a problem occurs in which thebattery power of the portable telephone is uselessly consumed.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provideda physical layer circuit for data transfer using a Universal Serial Bus(USB), the physical layer circuit comprising:

a VBUS detection circuit which monitors a voltage of a VBUS line of USB,and makes a VBUS detection signal active when the voltage of the VBUSline has exceeded a predetermined voltage;

a receiver circuit which receives first and second signals which aredifferential signals and performs reception processing using the firstand second signals; and

a reception control circuit which outputs a first enable signal to thereceiver circuit,

wherein the reception control circuit makes the first enable signalinactive and disables the receiver circuit when the VBUS detectionsignal is inactive.

According to a second aspect of the present invention, there is provideda physical layer circuit for data transfer using a Universal Serial Bus(USB), the physical layer circuit comprising:

a VBUS detection circuit which monitors a voltage of a VBUS line of USB,and makes a VBUS detection signal active when the voltage of the VBUSline has exceeded a predetermined voltage; and

a receiver circuit which receives first and second signals which aredifferential signals and performs reception processing using the firstand second signals,

wherein the VBUS detection circuit includes a first resistor providedbetween the VBUS line and a detection node and a second resistorprovided between the detection node and a node of a first power supply;and

wherein the VBUS detection circuit makes the VBUS detection signalactive when a voltage of the detection node has exceeded a predetermineddetection voltage.

According to a third aspect of the present invention, there is provideda data transfer control device, comprising:

any of the above-described physical layer circuits; and

a transfer controller which controls data transfer using USB.

According to a fourth aspect of the present invention, there is providedan electronic instrument, comprising:

the above-described data transfer control device; and

a processing section which controls the data transfer control device.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 shows a data transfer control device.

FIG. 2 shows a physical layer circuit.

FIG. 3 shows a VBUS detection circuit and a reception control circuit.

FIGS. 4A and 4B are illustrative of a sequence until USB data transferstarts.

FIG. 5 is illustrative of a resistor of a VBUS detection circuit.

FIG. 6 shows a differential receiver.

FIG. 7 shows a reference voltage generation circuit.

FIG. 8 shows a single end receiver.

FIG. 9 shows a detection buffer.

FIG. 10 shows an HS physical layer circuit.

FIGS. 11A and 11B are timing waveform charts showing a sequence from asuspend state to start of data transfer in a USB HS mode.

FIG. 12 shows an electronic instrument.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The following embodiments of the present invention may provide aphysical layer circuit and a data transfer control device which canreduce electric power uselessly consumed before the USB cable isconnected, and an electronic instrument having the data transfer controldevice.

According to one embodiment of the present invention, there is provideda physical layer circuit for data transfer using a Universal Serial Bus(USB), the physical layer circuit comprising:

a VBUS detection circuit which monitors a voltage of a VBUS line of USB,and makes a VBUS detection signal active when the voltage of the VBUSline has exceeded a predetermined voltage;

a receiver circuit which receives first and second signals which aredifferential signals and performs reception processing using the firstand second signals; and

a reception control circuit which outputs a first enable signal to thereceiver circuit,

wherein the reception control circuit makes the first enable signalinactive and disables the receiver circuit when the VBUS detectionsignal is inactive.

In this embodiment, the VBUS detection signal becomes active frominactive when the voltage of the VBUS line has exceeded a predeterminedvoltage, whereby the receiver circuit can be enabled. When the VBUSdetection signal is inactive, the first enable signal of the receivercircuit becomes inactive, whereby the receiver circuit is disabled. Thisprevents a problem in which electric power is uselessly consumed by thereceiver circuit before the connection of the USB cable, for example,whereby power consumption can be reduced.

In this physical layer circuit, the reception control circuit mayreceive a second enable signal set by a processing section; thereception control circuit may make the first enable signal inactive anddisable the receiver circuit when the second enable signal is active butthe VBUS detection signal is inactive; and the reception control circuitmay make the first enable signal active and enable the receiver circuitwhen the second enable signal and the VBUS detection signal are active.

This makes it possible to prevent the first enable signal of thereceiver circuit from becoming active unless the VBUS detection signalis made active, even if the second enable signal is made active by theprocessing section. This makes it possible the receiver circuit to bedisabled with certainty before the USB cable is connected, independentfrom the state of the second enable signal.

In this physical layer circuit, the VBUS detection circuit may include afirst resistor provided between the VBUS line and a detection node and asecond resistor provided between the detection node and a node of afirst power supply; and the VBUS detection circuit may make the VBUSdetection signal active when a voltage of the detection node hasexceeded a predetermined detection voltage.

According to one embodiment of the present invention, there is provideda physical layer circuit for data transfer using a Universal Serial Bus(USB), the physical layer circuit comprising:

a VBUS detection circuit which monitors a voltage of a VBUS line of USB,and makes a VBUS detection signal active when the voltage of the VBUSline has exceeded a predetermined voltage; and

a receiver circuit which receives first and second signals which aredifferential signals and performs reception processing using the firstand second signals,

wherein the VBUS detection circuit includes a first resistor providedbetween the VBUS line and a detection node and a second resistorprovided between the detection node and a node of a first power supply;and

wherein the VBUS detection circuit makes the VBUS detection signalactive when a voltage of the detection node has exceeded a predetermineddetection voltage.

By providing the first and second resistors in this manner, the firstand second resistors can be used as a voltage division resistor, acurrent limiting resistor and a pull-down resistor, for example.

In this physical layer circuit, VB×RV1/(RV1+RV2)<VR may be satisfied,where RV1 and RV2 represent resistances of the first and secondresistors, VB represents a voltage supplied to the VBUS line, and VRrepresents a rated voltage of the VBUS detection circuit.

This enables the rated voltage of the VBUS detection circuit to bemaintained, whereby reliability can be improved.

In this physical layer circuit, RV1+RV2>VB/IS may be satisfied, whereRV1 and RV2 represent resistances of the first and second resistors, VBrepresents a voltage supplied to the VBUS line, and IS represents anallowable value of current flowing from the VBUS line to the physicallayer circuit in suspend mode.

This makes it possible to deal with a demand relating to the standardfor the allowable value of the current which flowing from the VBUS lineto the physical layer circuit.

In this physical layer circuit, the receiver circuit may include adifferential receiver having first and second differential inputs towhich the first and second signals are respectively input; and a currentsource transistor of an operational amplifier circuit in thedifferential receiver may be turned OFF when the first enable signal isinactive.

This prevents an unnecessary current from flowing through thedifferential receiver before the USB cable is connected.

The physical layer circuit may further comprise a reference voltagegeneration circuit which outputs a reference voltage to the currentsource transistor, wherein an output node of the reference voltagegeneration circuit may be set to a power supply voltage and a currentflowing through the reference voltage generation circuit may beterminated, when the first enable signal is inactive.

This prevents an unnecessary current from flowing through thedifferential receiver and the reference voltage generation circuitbefore the USB cable is connected.

In this physical layer circuit, the reference voltage generation circuitmay include:

first and second transistors which are of a first conductivity type andform a current mirror circuit;

third transistor which is of a second conductivity type, connected inseries with the first transistor, and turned ON when the first enablesignal is active;

fourth transistor which is of the second conductivity type, connected inseries with the second transistor, and has a gate and a drain connectedto the output node of the reference voltage generation circuit; and

fifth transistor which is of the second conductivity type and providedbetween the output node and a node of a first power supply; and

wherein the third transistor may be turned OFF and the fifth transistormay be turned ON when the first enable signal is inactive.

This enables the output node of the reference voltage generation circuitto be set to the power supply voltage (or a voltage of the first orsecond power supply) and enables to terminate current flowing throughthe reference voltage generation circuit, with a simple configuration.

In this physical layer circuit,

the receiver circuit may include a first single end receiver having aninput to which the first signal is input, and a second single endreceiver having an input to which the second signal is input;

each of the first and second single end receivers may include a firstinverter circuit to which the first or second signal is input, and asecond inverter circuit having an input to which an output node of thefirst inverter circuit is connected; and

the output node of the first inverter circuit and an output node of thesecond inverter circuit may be set to a power supply voltage when thefirst enable signal is inactive.

This prevents a shoot-through current from occurring in the first andsecond inverter circuits and the like.

In this physical layer circuit,

the first inverter circuit may include:

a first transistor which is of a first conductivity type, providedbetween a node of a second power supply and a first intermediate node,and set to an ON state;

a second transistor which is of the first conductivity type, providedbetween the first intermediate node and the output node of the firstinverter circuit, and has a gate to which the first or second signal isinput;

a third transistor which is of a second conductivity type, providedbetween the output node and a second intermediate node, and has a gateto which the first or second signal is input;

a fourth transistor which is of the second conductivity type, providedbetween the second intermediate node and a node of a first power supply,and set to an ON state;

a fifth transistor which is of the first conductivity type, providedbetween the node of the second power supply and the first intermediatenode, and has a gate to which a feedback signal from the second invertercircuit is input;

a sixth transistor which is of the first conductivity type and providedbetween the first intermediate node and the output node; and

a seventh transistor which is of the second conductivity type, providedbetween the second intermediate node and the node of the first powersupply, and has a gate to which the feedback signal is input; and

the sixth transistor may be turned ON when the first enable signal isinactive.

This enables the output node of the first inverter circuit to be set tothe power supply voltage by effectively utilizing the first transistorset to the ON state and the sixth transistor which is turned ON when theenable signal is inactive.

In this physical layer circuit, the receiver circuit may be a USB fullspeed receiver circuit.

According to one embodiment of the present invention, there is provideda data transfer control device, comprising: any of the above-describedphysical layer circuits; and a transfer controller which controls datatransfer using USB.

According to one embodiment of the present invention, there is providedan electronic instrument, comprising: the above-described data transfercontrol device; and a processing section which controls the datatransfer control device.

These embodiments will be described in detail below. Note that theembodiments described below do not in any way limit the scope of theinvention laid out in the claims herein. In addition, not all of theelements of the embodiments described below should be taken as essentialrequirements of the present invention.

-   1. Data Transfer Control Device

FIG. 1 shows a data transfer control device according to one embodimentof the present invention. The data transfer control device shown in FIG.1 includes a transceiver 200, a transfer controller 210, a buffercontroller 220, a data buffer 230, and an interface circuit 240. Some ofthese circuit blocks may be omitted, or the connection configuration ofthe circuit blocks may be changed, or another circuit block may beadded. For example, the data transfer control device may have aconfiguration in which the buffer controller 22, the data buffer 230,and the interface circuit 240 are omitted.

The transceiver 200 is a circuit for transmitting and receiving datausing differential signals DP and DM (differential data signals). Thetransceiver 200 includes a USB (given interface standard in a broadsense) physical layer circuit (analog front-end circuit), for example. Acircuit in a layer other than the physical layer may be included in thetransceiver 200.

The transfer controller 210 is a controller for controlling datatransfer through the USB, and implements a function of a serialinterface engine (SIE) or the like. The transfer controller 210 performspacket handling processing, suspend & resume control, or transactionmanagement, for example.

The buffer controller 220 allocates a storage region (endpoint region orthe like) in a data buffer 230, and controls access to the storageregion of the data buffer 230. In more detail, the buffer controller 220controls access from the application layer device through the interfacecircuit 240, access from the CPU through the interface circuit 240, oraccess from the USB (transfer controller 210), arbitrates theseaccesses, or generates and manages access addresses.

The data buffer 230 (packet buffer) is a buffer (FIFO) for temporarilystoring (buffering) data (transmission data or reception data)transferred through the USB. The data buffer 230 may be formed by amemory such as a RAM.

The interface circuit 240 is a circuit for implementing an interfacethrough a direct memory access (DMA) bus to which the application layerdevice is connected and a CPU bus to which the CPU is connected. Theinterface circuit 240 may include a DMA handler circuit for DMAtransfer, for example.

-   2. Transceiver

FIG. 2 shows a physical layer circuit included in the transceiver 200.

In FIG. 2, the transmitter circuit 10 is a circuit for performing datatransmission processing using the differential signals DP and DM in theUSB FS mode, for example. The transmitter circuit 10 includes a firsttransmission driver 12 which drives a signal line for the signal DP(first signal in a broad sense) which makes up the differential signals,and a second transmission driver 14 which drives a signal line for thesignal DM (second signal in a broad sense) which makes up thedifferential signals. The differential signals can be transferred bydriving the signal lines for the signals DP and DM by the transmissiondrivers 12 and 14.

The transmitter circuit 10 includes a first damping resistor RDP1 and asecond damping resistor RDP2 respectively connected with the signallines (pads) for the signals DP and DM. One end of the damping resistorsRDP1 and RDP2 is respectively connected with the outputs of thetransmission drivers 12 and 14. and the other end is respectivelyconnected with the signal lines for the signals DP and DM. Thetransmitter circuit 10 (integrated circuit device) may have aconfiguration in which the damping resistors RDP1 and RDP2 are omitted.In this case, the damping resistors RDP1 and RDP2 may be implemented byexternal parts.

First and second transmission control circuits 22 and 24 are circuitsfor controlling the first and second transmission drivers 12 and 14. Inmore detail, the transmission control circuit 22 receives a transmissiondata signal DOUT1 and an output disable signal OUTDIS from the circuitin the previous stage (circuit in the macrocell MC2, for example), andoutputs control signals OP1 and ON1 to the transmission driver 12. Thetransmission control circuit 24 receives signals DOUT2 and OUTDIS fromthe circuit in the previous stage, and outputs control signals OP2 andON2 to the transmission driver 14.

A receiver circuit 30 is a circuit to which the signals DP and DM (firstand second signals) forming the differential signals are input and whichperforms reception processing using the signals DP and DM in the USB FSmode, for example. The receiver circuit 30 includes a differentialreceiver 32, and first and second single end receivers 34 and 36.

The differential receiver 32 (differential comparator) differentiallyamplifies the differential signals input through the signal lines forthe signals DP and DM, and outputs the amplified signal to the circuitin the next stage (circuit in the macrocell MC2, for example) as a datasignal DIN. The differential receiver 32 may be implemented by anoperational amplifier circuit having first and second differentialinputs to which the signals DP and DM are input. The operation of thedifferential receiver 32 is enabled or disabled by an enable signalCOMPENB.

The single end receiver 34 amplifies the single end signal input throughthe signal line for the signal DP, and outputs the amplified signal tothe circuit in the next stage (circuit in the macrocell MC2, forexample) as a data signal SEDIN1. The single end receiver 36 amplifiesthe single end signal input through the signal line for the signal DM,and outputs the amplified signal to the circuit in the next stage as adata signal SEDIN2. The single end receivers 34 and 36 may beimplemented by buffer circuits having hysteresis characteristics inwhich the threshold voltage differs between the rising time and thefalling time of the input voltage, for example. The operations of thesingle end receivers 34 and 36 are enabled or disabled by enable signalsSEENB1 and SEENB2.

A pull-up resistor circuit 40 is a circuit for pulling up the signalline for the signal DP. The resistor circuit 40 includes a switchelement SUP1 implemented by a transistor or the like, and a 1.5 Kohmpull-up resistor RUP1, for example. In more detail, one end of theswitch element SUP1 is connected with the signal line for the signal DP,and the other end is connected with one end of a resistor RUP1. Theother end of the resistor RUP1 is connected with a power supply VDD.

A resistor circuit 42 is a dummy resistor circuit for forming, on thesignal line for the signal DM, a parasitic capacitance equivalent to aparasitic capacitance formed by connecting the resistor circuit 40 withthe signal line for the signal DP or the like. The resistor circuit 42includes a switch element SUP2 and a resistor RUP2 respectively havingthe same configuration as the switch element SUP1 and the resistor RUP1of the resistor circuit 40 (same gate length and gate width, and sameresistance). In more detail, one end of the switch element SUP2 isconnected with the signal line for the signal DM, and the other end isconnected with one end of a resistor RUP2.

In FIG. 3, the resistors RUP1 and RUP2 are provided on the side of thepower supply VDD. However, the switch elements SUP1 and SUP2 may beprovided on the side of the power supply VDD.

Resistor control circuits 50 and 52 are circuits for respectivelycontrolling the resistor circuits 40 and 42. In more detail, theresistor control circuits 50 and 52 generate signals RUPSW1 and RUPSW2which control ON/OFF of the switch elements SUP1 and SUP2, and outputthe signals RUPSW1 and RUPSW2 to the resistor circuits 40 and 42,respectively.

The resistor control circuit 50 outputs the signal RUPSW1 based on apull-up enable signal RUPENB from the circuit in the previous stage(circuit in the macrocell MC2, for example) to ON/OFF control the switchelement SUP1. The resistor control circuit 52 outputs the signal RUPSW2based on a pull-up enable signal RUPENB2 from the circuit in theprevious stage to ON/OFF control the switch element SUP2.

A VBUS detection circuit 100 monitors the voltage of the USB VBUS line(power supply line in a broad sense), and makes a VBUS detection signalVBDET active (high level, for example) when the voltage of the VBUS linehas exceeded a predetermined voltage (operation effective voltages suchas 4.4 V or 4.65 V, for example).

A reception control circuit 110 is a circuit which controls enabling anddisabling of the receiver circuit 30. In more detail, the receptioncontrol circuit 110 receives the VBUS detection signal VBDET from theVBUS detection circuit 100. When the VBUS detection signal VBDET isinactive (low level, for example), the reception control circuit 110makes the enable signals COMPENB, SEENB1 and SEENB2 output to thereceiver circuit 30 inactive to disable the receiver circuit 30.Specifically, the reception control circuit 110 disables thedifferential receiver 32, the first single end receiver 34, and thesecond single end receiver 36 by the signals COMPENB, SEENB1, andSEENB2, respectively. When the VBUS detection signal VBDET is inactive,the receiver circuit 30 may be disabled by a signal set by a processingsection (firmware).

-   3. VBUS detection circuit and Reception Control Circuit

FIG. 3 shows the VBUS detection circuit 100 and the reception controlcircuit 110. The VBUS detection circuit 100 and the reception controlcircuit 110 in this embodiment are not limited to the configurationshown in FIG. 3. Some of the circuit elements shown in FIG. 3 may beomitted, or the connection configuration of the circuit elements may bechanged, or a circuit element differing from the elements shown in FIG.3 may be added.

The VBUS detection circuit 100 includes first and second resistors R1and R2 connected in series, and a detection buffer 102. In more detail,the resistor R1 is provided between the VBUS line (VBUS pad) and adetection node NDET. The resistor R2 is provided between the detectionnode NDET and a node of a power supply VSS (first power supply in abroad sense). This causes a voltage VD obtained by dividing the VBUSvoltage by the resistors R1 and R2 to be generated at the detection nodeNDET.

When the voltage VD of the detection node NDET has exceeded apredetermined detection voltage, the detection buffer 102 makes the VBUSdetection signal VBDET active (high level). The detection buffer 102 isa buffer which changes the voltage level of the VBUS detection signalVBDET when the voltage VD of the detection node NDET has exceeded athreshold voltage of the detection buffer 102, and may be implemented bya buffer having hysteresis characteristics relating to the thresholdvoltage, for example.

The reception control circuit 110 receives the VBUS detection signalVBDET from the VBUS detection circuit 100 and second enable signalsFCOMPENB, FSEENB1, and FSEENB2. The reception control circuit 110outputs the enable signals COMPENB, SEENB1, and SEENB2 to thedifferential receiver 32 and the single end receivers 34 and 36 of thereceiver circuit 30.

The second enable signals FCOMPENB, FSEENB1, and FSEENB2 are signals setby the processing section (CPU and firmware) which controls the datatransfer control device. In more detail, the signals FCOMPENB, FSEENB1,and FSEENB2 are output from a control register included in the datatransfer control device. The processing section writes information forenabling or disabling the differential receiver 32 and the single endreceivers 34 and 36 into the control register. For example, wheninformation for enabling the differential receiver 32 and the single endreceivers 34 and 36 is written into the control register by theprocessing section, the signals FCOMPENB, FSEENB1, and FSEENB2 becomeactive (high level). When information for disabling the differentialreceiver 32 and the single end receivers 34 and 36 is written into thecontrol register by the processing section, the signals FCOMPENB,FSEENB1, and FSEENB2 become inactive (low level).

The reception control circuit 110 calculates the logical AND of the VBUSdetection signal VBDET and the second enable signals FCOMPENB, FSEENB1,and FSEENB2, for example, and outputs the resulting enable signalsCOMPENB, SEENB1, and SEENB2. The logical AND calculation is implementedby an AND1 circuit, an AND2 circuit, and an AND3 circuit (logic circuitsor logical AND logic circuits in a broad sense) having first inputs towhich the VBUS detection signal VBDET is input and also having secondinputs to which the signals FCOMPENB, FSEENB1, and FSEENB2 are input.

This makes the enable signals COMPENB, SEENB1 and SEENB2 output to thereceiver circuit 30 inactive (low level) when the VBUS detection signalVBDET is inactive (low level), even if the second enable signalsFCOMPENB, FSEENB1, and FSEENB2 are active (high level). The differentialreceiver 32 and the single end receivers 34 and 36 of the receivercircuit 30 are disabled.

When the second enable signals FCOMPENB, FSEENB1, and FSEENB2 and theVBUS detection signal VBDET are active (high level), the enable signalsCOMPENB, SEENB1, and SEENB2 become active (high level). This enables thedifferential receiver 32 and the single end receivers 34 and 36 of thereceiver circuit 30.

In FIG. 3, the signals SEENBI and SEENB2 for the single end receivers 34and 36 may be one common signal, and the signals FSEENB1 and FSEENB2 maybe one common signal. Specifically, the reception control circuit 110may control enabling and disabling of the single end receivers 34 and 36by receiving one signal FSEENB and outputting one signal SEENB to thesingle end receivers 34 and 36. In this case, only two AND circuits maybe provided in the reception control circuit 110. The signals COMPENB,SEENB1, and SEENB2 may be one common signal, and the signals FCOMPENB,FSEENB1, and FSEENB2 may be one common signal. For example, thereception control circuit 110 may control enabling and disabling of thedifferential receiver 32 and the single end receivers 34 and 36 byreceiving one signal FRENB and outputting one signal RENB to thedifferential receiver 32 and the single end receivers 34 and 36. In thiscase, only one AND circuit may be provided in the reception controlcircuit 110.

-   4. Disabling of Receiver Circuit

A sequence from a suspend state until FS data transfer is started in USBis described below with reference to FIGS. 4A and 4B.

When the data transfer control device (electronic instrument) standsready in the suspend state (step S1), the power supply is started toVBUS when the USB cable is connected, whereby the suspend state iscanceled (step S2). As shown in FIG. 4B, the host side pulls down thesignal line for the signals DP and DM and the device side pulls up thesignal line for the signal DP (step S3). For example, in FIG. 2, thedata transfer control device on the device side turns ON the switch SUP1to pull up the signal line for the signal DP.

The single end receiver detects the FS J state (step S4). Specifically,the single end receiver 34 shown in FIG. 2 detects whether or not thesignal line for the signal DP is at an appropriate pull-up voltage. Thesingle end receiver 36 detects whether or not the signal line for thesignal DM is at an appropriate pull-down voltage. When the FS J state(pull-up of DP and pull-down of DM) has been detected, an FS datatransfer using the differential receiver 32 starts (step S5).

As shown in FIG. 4A, the USB data transfer control device starts thedata transfer operation (detection of FS J state and FS data transfer)after the USB cable has been connected and the power supply is startedto VBUS (after the VBUS voltage has risen). Therefore, unnecessaryelectric power is consumed if electric power is consumed by the receivercircuit 30 before the USB cable is connected.

However, in a conventional data transfer control device, the receivercircuit 30 is also enabled before the USB cable is connected. Therefore,an unnecessary current flows through the receiver circuit 30 before theUSB cable is connected, whereby a reduction of power consumption ishindered.

Before the USB cable is connected, the signal lines for the signals DPand DM are in a floating state in which no signal is supplied. Since thesignal lines for the signals DP and DP in the floating state areconnected to gates of transistors forming circuits disposed in the firststage of the single end receivers 34 and 36, a problem occurs in which ashoot-through current flows through the circuits in the first stage.

In this embodiment, the VBUS detection circuit 100 and the receptioncontrol circuit 110, which are not provided in a conventional datatransfer control device, are additionally provided. The VBUS detectioncircuit 100 detects whether or not the voltage of the VBUS line hasexceeded a predetermined voltage, and outputs the VBUS detection signal.When the VBUS detection signal is inactive, the reception controlcircuit 110 makes the enable signals COMPENB, SEENB1 and SEENB2 inactiveto disable the receiver circuit 30.

This enables the receiver circuit to be disabled with certainty by thehardware circuit (VBUS detection circuit 100 and reception controlcircuit 110) before the USB cable is connected. Therefore, a problem inwhich an unnecessary current flows through the receiver circuit 30before the USB cable is connected can be prevented. Moreover, since thesingle end receivers 34 and 36 are disabled even if the signal lines forthe signals DP and DM are in the floating state before the USB cable isconnected, a problem in which a shoot-through current flows through thecircuits in the first stage can be prevented, whereby power consumptioncan be reduced. For example, when the data transfer control device inthis embodiment (physical layer circuit) is incorporated into a portabletelephone having a USB interface, a problem in which the battery of theportable telephone is unnecessarily consumed when the USB cable is notconnected can be prevented.

According to this embodiment, as shown in FIG. 3, even if the secondenable signals FCOMPENB, FSEENB1 and FSEENB2 are made active by theprocessing section, when the VBUS detection signal VBDET is inactive,the enable signals COMPENB, SEENB1, and SEENB2 become inactive, wherebythe receiver circuit 30 is disabled. This enables the receiver circuit30 to be disabled by the hardware circuit before the USB cable isconnected independent from the setting by the processing section.

As is clear from the USB sequence shown in FIG. 4A, after the USB cablehas been connected, the single end receivers 34 and 36 detect the FS Jstate before the data transfer starts. Therefore, the firmware of theprocessing section enables the single end receivers 34 and 36 before theUSB cable is connected and allows the single end receivers 34 and 36 tobe in the standby state. In particular, a self-powered data transfercontrol device operation can operate by its own power supply even ifelectric power is not supplied to VBUS. Therefore, the firmware maylikely make the signals FCOMPENB, FSEENB1 and FSEENB2 active before theUSB cable is connected.

According to this embodiment, even if the signals FCOMPENB, FSEENB1 andFSEENB2 are made active by the firmware, the signals COMPENB, SEENB1,and SEENB2 do not become active as long as the signal VBDET does notbecome active. Therefore, the receiver circuit 30 can be disabled by thehardware circuit with certainty before the USB cable is connected,whereby a highly reliable power management can be implemented.

It suffices that the single end receivers 34 and 36 be enabled at leastbefore the step S4 in FIG. 4A, and that the differential receiver 32 beenabled at least before the step S5. Therefore, it suffices that thefirmware of the processing section enable the single end receivers 34and 36 by causing the signals FSEENB1 and FSEENB2 to become activebefore the step S4. It suffices that the firmware enables thedifferential receiver 32 by causing the signal FSCOMPENB to becomeactive. This further reduces power consumption.

-   5. Resistor of VBUS detection circuit

As shown in FIG. 5, the VBUS detection circuit 100 in this embodimentdivides the VBUS supply voltage VB by the resistors R1 and R2. Theresulting divided voltage VD is input to the detection buffer 102. Thisleads to the following advantages.

Since the integrated circuit device which implements the data transfercontrol device (physical layer circuit) has been reduced in size, thepower supply voltage is as low as 3.3 V or 1.8 V, whereby the ratedvoltage VR (maximum rated voltage) of the detection buffer 102 shown inFIG. 5 is decreased. On the other hand, since the VBUS supply voltage VBis 5 V at a typical value, if the supply voltage VB of 5 V is directlyinput to the detection buffer 102, the rated voltage VR of the detectionbuffer 102 cannot be maintained.

In FIG. 5, the voltage VD obtained by dividing the VBUS supply voltageVB by the resistors R1 and R2 is input to the detection buffer 102.Therefore, if the resistors R1 and R2 are set so that the dividedvoltage VD is lower than the rated voltage of the detection buffer 102,the rated voltage VR of the detection buffer 102 can be kept. In thiscase, when the resistances of the resistors R1 and R2 are denoted by RV1and RV2, the voltage supplied to the VBUS line is denoted by VB, and therated voltage of the detection buffer 102 (VBUS detection circuit) isdenoted by VR, it is preferable that the following relational formula besatisfied.VD=VB×RV1/(RV1+RV2)<VR  (1)

In USB, an allowable value (maximum value) IS of current which flowstoward the physical layer circuit (data transfer control device) throughthe VBUS line in the suspend state is standardized such as IS=500 μA.This reduces an unnecessary current which flows through the VBUS line inthe suspend state as much as possible in a self-powered data transfercontrol device which does not require a power supply to VBUS, wherebypower consumption of the entire system can be reduced.

Therefore, in FIG. 5, the resistors R1 and R2 are provided between theVBUS line and the power supply VSS. A current which flows toward thepower supply VSS through the VBUS line can be limited by providing theresistors R1 and R2. This makes it possible to satisfy a requirement inthe USB standard relating to the current allowable value IS in thesuspend state (IS=500 μA). In this case, when the resistances of theresistors R1 and R2 are denoted by RV1 and RV2, the voltage supplied tothe VBUS line is denoted by VB, and the allowable value of current whichflows toward the physical layer circuit (data transfer control device )through the VBUS line is denoted by IS, it is preferable that thefollowing relational formula be satisfied.RV1+RV2>VB/IS  (2)

The VBUS line is in a floating state in which no signal is suppliedbefore the USB cable is connected. Therefore, if a configuration inwhich the VBUS line is directly connected with the detection buffer 102is employed, the VBUS line in the floating state is connected with thegate of the transistor which makes up the circuit in the first stage ofthe detection buffer 102, whereby a shoot-through current occurs in thecircuit in the first stage.

In FIG. 5, since electric power is not supplied to VBUS before the USBcable is connected, the resistor R2 functions as a pull-down resistor.Therefore, the voltage of the detection node NDET is set to the voltageof the power supply VSS (0 V) by pulling down before the USB cable isconnected. As a result, the voltage VSS is input to the gate of thetransistor which makes up the circuit in the first stage of thedetection buffer 102, whereby a problem in which a shoot-through currentoccurs in the circuit in the first stage can be prevented.

As described above, according to the configuration shown in FIG. 5, theresistors R1 and R2 can have the role as the voltage division resistorsfor maintaining the rated voltage of the detection buffer 102, the roleas the current limiting resistor for satisfying the demand in the USBstandard relating to the current allowable value IS, and the role as thepull-down resistors for preventing occurrence of a shoot-through currentwhich flows through the circuit in the first stage of the detectionbuffer 102. Therefore, a specific effect differing from the conventionalexample can be obtained.

-   6. Differential Receiver

FIG. 6 shows the differential receiver 32 (for FS). The differentialreceiver 32 includes operational amplifier circuits 120 and 122, anoutput circuit 124, inverter circuits 126 and 128, and a referencevoltage generation circuit 130. The differential receiver 32 may have aconfiguration in which some of these circuits are omitted.

The operational amplifier circuit 120 includes P-type (firstconductivity type in a broad sense; hereinafter the same) transistorsTA1 and TA2 forming a current mirror circuit, N-type (secondconductivity type in a broad sense; hereinafter the same) transistorsTA3 and TA4 forming a differential pair, and an N-type transistor TA5forming a current source. The operational amplifier circuit 122 includesP-type transistors TA6 and TA7 forming a current mirror circuit, N-typetransistors TA8 and TA9 forming a differential pair, and an N-typetransistor TA10 forming a current source. The output circuit 124includes a P-type drive transistor TA11, and an N-type transistor TA12which is connected in series with the transistor TA11 and makes up acurrent source. The output circuit 124 includes a P-type transistor TA13for setting an output node NA5 of the output circuit 124 at a powersupply voltage (VDD) when the enable signal ENB (COMPENB) is at the lowlevel (inactive).

The signals DP and DM (first and second signals) are input to gates ofthe transistor TA3 and TA4, which are first and second differentialinputs of the operational amplifier circuit 120. Output signals fromoutput nodes NA2 and NA1 of the operational amplifier circuit 120 areinput to gates of the transistors TA8 and TA9 which are first and seconddifferential inputs of a calculation circuit 122. An output signal froman output node NA4 of the calculation circuit 122 is input to a gate ofthe transistor TA11 of an output circuit 124. An output signal from theoutput node NA5 of the output circuit 124 is buffered by an invertercircuit 128 formed by an inverter circuit 126 formed by transistors TA14and TA15 and transistors TA16 and TA17, and output as a signal DIN. Inthis embodiment, the voltages denoted by VDD and VSS need not be thesame voltage. For example, the voltage VDD of the inverter circuits 126and 128 shown in FIG. 6 may be set to be lower than the voltage VDD ofthe operational amplifier circuits 120 and 122.

A reference voltage generation circuit 130 receives a comparator enablesignal COMPENB, and outputs a reference voltage VREF and an enablesignal ENB. The output reference voltage VREF is input to gates of thetransistors TA5, TA10, and TA12 forming a current source. The enablesignal ENB is input to a gate of the transistor TA13 of the outputcircuit 124.

According to the differential receiver 32 shown in FIG. 6, when theenable signal COMPENB is set to the low level (inactive), the referencevoltage VREF is set to the power supply voltage (VSS), whereby thecurrent source transistors TA5 and TA10 of the operational amplifiercircuits 120 and 122 are turned OFF. The current source transistor TA12of the output circuit 124 is also turned OFF. This terminates currentwhich flows through the operational amplifier circuits 120 and 122,whereby power consumption can be reduced.

Moreover, since the transistor TA13 is turned ON when the enable signalCOMPENB is set to the low level, whereby the output node NA5 of theoutput circuit 124 is set to the power supply voltage (VDD). Thisprevents a problem in which a shoot-through current flows through theinverter circuits 126 and 128 can be prevented. Specifically, if thetransistor TA13 is not provided, the output node NA5 is set to thefloating state in which no voltage is supplied when the current sourcetransistor TA12 is turned OFF, whereby a shoot-through current flowsthrough the inverter circuits 126 and 128. Since the output node NA5 isset to the power supply voltage (VDD) by providing the transistor TA13,such a problem can be prevented.

FIG. 7 shows the reference voltage generation circuit 130. The referencevoltage generation circuit 130 includes P-type (first conductivity type)transistors TB1 and TB2 forming a current mirror circuit. The referencevoltage generation circuit 130 also includes an N-type (secondconductivity type) transistor TB3 which is connected in series with thetransistor TB1 and is turned ON when the enable signal COMPENB isactive. The reference voltage generation circuit 130 also includes anN-type transistor TB4 which is connected in series with the transistorTB2 and is connected with an output node NB2 of the reference voltagegeneration circuit 130 at its gate and drain. The reference voltagegeneration circuit 130 also includes an N-type transistor TB5 providedbetween the output node NB2 and the power supply VSS.

When the signal COMPENB is set to the high level (active), thetransistor TB3 is turned ON. This causes current which flows through thetransistors TB1 and TB3 to flow through the transistors TB2 and TB4 bythe current mirror, whereby the reference voltage VREF occurs at theoutput node NB2. When the signal COMPENB is set to the low level(inactive), the transistor TB3 is turned OFF and the transistor TB5 isturned ON.

According to the reference voltage generation circuit 130 shown in FIG.7, since the transistor TB5 is turned ON when the enable signal COMPENBis set to the low level, the output node NB5 is set to the power supplyvoltage (VSS). This causes the transistors TA5, TA10, and TA12 shown inFIG. 6 to be turned OFF, whereby power consumption can be reduced. Whenthe enable signal COMPENB is set to the low level, the transistors TB1to TB4 are turned OFF and the transistor TB5 is turned ON. Thisterminates current which flows through the reference voltage generationcircuit 130, whereby power consumption can be reduced.

-   7. Single End Receiver

FIG. 8 shows the single end receiver 34. The configuration of the singleend receiver 36 is the same as the configuration of the single endreceiver 34. Therefore, description is omitted.

The single end receiver 34 includes a first inverter circuit 140 towhich the signal DP (signal DM in the single end receiver 36) is input,and a second inverter circuit 141 having an input to which an outputnode NC1 of the first inverter circuit 140 is connected.

The inverter circuit 140 includes transistors TC1, TC2, TC3, and TC4connected in series between the power supplies VDD and VSS.

In more detail, the inverter circuit 140 includes the P-type (firstconductivity type) transistor TC1 provided between a node of the secondpower supply VDD and a first intermediate node NMC1. The transistor TC1is always set in the ON state by inputting the voltage of the powersupply VSS to a gate of the transistor TC1. The inverter circuit 140includes the P-type transistor TC2 which is provided between theintermediate node NMC1 and the output node NC1 and has a gate to whichthe signal DP (DM) is input. The inverter circuit 140 includes theN-type (second conductivity type) transistor TC3 which is providedbetween the output node NC1 and a second intermediate node NMC2 and hasa gate to which the signal DP (DM) is input. The inverter circuit 140includes the N-type transistor TC4 provided between the node of thefirst power supply VSS and the second intermediate node NMC2. Thetransistor TC4 is always set in the ON state by inputting the voltage ofthe power supply VDD to a gate of the transistor TC4.

The inverter circuit 140 includes transistors TC5, TC6, and TC7 whichare respectively connected in parallel with the transistors TC1, TC2,and TC4.

In more detail, the inverter circuit 140 includes the P-type transistorTC5 which is provided between the node of the power supply VDD and theintermediate node NMC1 and has a gate to which a feedback signal FESfrom the inverter circuit 141 is input. The inverter circuit 140includes the P-type transistor TC6 provided between the intermediatenode NMC1 and the output node NC1. The inverter circuit 140 includes theN-type transistor TC7 which is provided between the intermediate nodeNMC2 and the node of the power supply VSS and has a gate to which thefeedback signal FES is input.

The inverter circuit 141 includes P-type transistors TC8 and TC9connected in series between the node of the power supply VDD and anoutput node NC2. The inverter circuit 141 includes an N-type transistorTC10 provided between the output node NC2 and the node of the powersupply VSS. The inverter circuit 141 includes an N-type transistor TC11provided in parallel with the transistor TC10 between the output nodeNC2 and the node of the power supply VSS. An inversion signal of theenable signal SEENB1 (SEENB2) is input to the gates of the transistorsTC8 and TC11. The output node NC1 of the inverter circuit 140 isconnected with the gates of the transistors TC9 and TC10. The outputsignal from the output node NC2 of the inverter circuit 141 is bufferedby the inverter circuit 142 formed by transistors TC12 and TC13 and aninverter circuit 144 formed by transistors TC14 and TC15, and is outputas the signal SEDIN1 (SEDIN2).

In FIG. 8, when the signal DP (DM) is at the low level, the voltage ofthe output node NC2 is set to the low level. This causes the transistorTC5 to be turned ON, whereby the on-resistance of the P-type transistoris decreased. This increases the threshold voltage when the signal DP(DM) changes from the low level to the high level. When the signal DP(DM) is at the high level, the voltage of the output node NC2 is set tothe high level. This causes the transistor TC7 to be turned ON, wherebythe on-resistance of the N-type transistor is decreased. This decreasesthe threshold voltage when the signal DP (DM) changes from the highlevel to the low level. The hysteresis characteristics relating to thethreshold voltage are implemented in this manner.

In FIG. 8, the transistor TC6 is turned ON when the enable signal SEENB1(SEENB2) is set to the low level (inactive), whereby the output node NC1of the inverter circuit 140 is set to the voltage of the power supplyVDD. Specifically, the transistor TC1 is always set in the ON state inFIG. 8 in order to implement the hysteresis characteristics relating tothe threshold voltage. Therefore, the node of the power supply VDD andthe output node NC1 are electrically connected when the transistor TC6is turned ON, whereby the output node NC1 is set to the voltage of thepower supply VDD. In FIG. 8, the output node NC1 is set to the powersupply voltage by effectively utilizing the transistor TC1 set to the ONstate as described above.

The transistor TC11 is turned ON when the enable signal SEENB1 is set tothe low level, whereby the output node NC2 of the inverter circuit 141is set to the voltage of the power supply VSS. The transistor TC8 isturned OFF, whereby current which flows through the path of thetransistors TC8, TC9, and TC10 of the inverter circuit 141 isterminated.

The signal lines for the signals DP and DM are in the floating state inwhich no signal is supplied before the USB cable is connected.Therefore, if the signal lines for the signals DP and DM in the floatingstate are connected with the transistors TC2 and TC3 of the invertercircuit 140, a shoot-through current may occur in the inverter circuit140. A shoot-through current may also occur in the inverter circuits141, 142, and 144 in the next stage due to unstable voltages of theoutput nodes NC1 and NC2.

In FIG. 8, when the enable signal SEENB1 (SEENB2) is set to the lowlevel, the output nodes NC1 and NC2 of the inverter circuits 140 and 141are set to the power supply voltages (voltages of the power supplies VDDand VSS). Therefore, a problem in which a shoot-through current occursin the inverter circuits 140, 141, 142, and 144 can be prevented bysetting the enable signals SEENB1 and SEENB2 at the low level before theUSB cable is connected, whereby power consumption can be reduced.

FIG. 9 shows the detection buffer 102 shown in FIG. 3. The detectionbuffer 102 shown in FIG. 9 has approximately the same configuration asthe configuration of the single end receiver 34 shown in FIG. 8. Thedetection buffer 102 differs from the single end receiver 34 in thattransistors corresponding to the transistors TC6, TC8, and TC11 shown inFIG. 8 are omitted in FIG. 9.

The resistance to signal noise is increased by using the detectionbuffer 102 having hysteresis characteristics relating to the thresholdvoltage as shown in FIG. 9, whereby the VBUS voltage can be detectedwith higher reliability and certainty.

-   8. HS Mode

The full speed (FS) mode in which data is transferred at 12 Mbps isdefined in USB. In USB 2.0, the high speed (HS) mode at a transfer rateof 480 Mbps is defined in addition to the FS mode. The method in thisembodiment may also be applied to an FS receiver circuit of a physicallayer circuit which supports the HS mode.

FIG. 10 shows a physical layer circuit for implementing the USB 2.0 HSmode. FIG. 10 differs from FIG. 2 in that an HS transmitter circuit 70,transmission control circuits 82 and 84, an HS receiver circuit 90, anda detection circuits 98 are further provided in FIG. 10.

The HS transmitter circuit 70 is connected with the signal lines for thesignals DP and DM, and includes a current source 76 (constant currentsource) and first and second transmission drivers 72 and 74 (currentdrivers). The current source 76 supplies current to the transmissiondrivers 72 and 74 when the enable signal HSENB becomes active.

The HS first and second transmission control circuits 82 and 84 arecircuits for controlling first and second transmission drivers 72 and74. In more detail, the transmission control circuit 82 receives atransmission data signal HSDOUT1 and an output disable signal HSOUTDISfrom the circuit in the previous stage, and outputs a control signal GC1to the transmission driver 72. The transmission control circuit 84receives signals HSDOUT2 and HSOUTDIS from the circuit in the previousstage, and outputs a control signal GC2 to the transmission driver 74.

The receiver circuit 90 is a circuit for performing reception processingin the USB HS mode, and includes a differential receiver 92. Thedifferential receiver 92 (differential comparator) differentiallyamplifies the differential signals input through the signal lines forthe signals DP and DM, and outputs the amplified signal to the circuitin the next stage as a data signal HSDIN. The differential receiver 92may be implemented by an operational amplifier circuit having first andsecond differential inputs to which the differential signals DP and DMare input. The operation of the differential receiver 92 is enabled ordisabled by an enable signal HSCOMPENB.

The detection circuit 98 (squelch circuit) is a circuit fordistinguishing whether the signal (DP and DM) on the USB is effectivedata or noise. In more detail, the detection circuit 98 detects theamplitude of the signal by holding the peak value of the USB signal anddetecting the envelope of the signal. For example, the detection circuit98 judges that the signal is noise when the amplitude is 100 mV or less,and judges that the signal is effective data when the amplitude is 150mV or more. When the detection circuit 98 judges that the signal iseffective data, the detection circuit 98 makes an output signal HSSQactive. The operation of the detection circuit 98 is enabled or disabledby an enable signal HSSQENB.

As shown in FIG. 10, the VBUS detection circuit 100 and the receptioncontrol circuit 110 as shown in FIG. 2 may be provided in such an HSmode physical layer circuit. When the VBUS detection signal VBDET isinactive, the reception control circuit 110 makes the signals COMPENB,SEENB1 and SEENB2 inactive to disable the FS receiver circuit 30.

FIGS. 11A and 11B are timing waveform charts showing a sequence from thesuspend state to the start of data transfer in the USB HS mode.

When the VBUS voltage rises as indicated by A1 shown in FIG. 11A, theVBUS detection signal VBDET is set to the high level (active) asindicated by A2. This allows the receiver circuit 30 to be enabled.

As indicated by A3 shown in FIG. 11A, the single end receivers 34 and 36detect that the line state is an FS J state. It suffices that the singleend receivers 34 and 36 be enabled before a timing T1 at which thedetection processing of the FS J state starts. When a reset (SE0) issent from a downstream port, an HS detection handshake starts at atiming T2.

When the HS detection handshake has started, the HS transmitter circuitand receiver circuit are enabled, whereby a chirp (K) starts to be sentas indicated by A5 shown in FIG. 11B.

After sending of the chirp (K) has been completed, the transmission ofthe chirp (K) starts at a timing T3 when a downstream port supports theHS mode, whereby data transfer in the HS mode can be achieved. However,since the chirp cannot be detected before a timing T4 in FIG. 11B, thedata transfer control device returns to the FS mode, and waits forcompletion of the reset sequence. The reset sequence ends at a timingT5, and data transfer in the FS mode starts at a timing T6. If adownstream port chirp is sent, data transfer in the HS mode can bestarted at the timing T6.

In USB 2.0 which supports the HS mode, the FS J state is detected by theFS receiver circuit 30 before the HS detection handshake. Therefore, ina conventional method, the FS receiver circuit 30 is enabled before theUSB cable is connected and the VBUS voltage is supplied, wherebyunnecessary electric power is consumed by the receiver circuit 30.

In this embodiment, the FS receiver circuit 30 can be enabled oncondition that the VBUS detection signal VBDET has become active asindicated by A2 shown in FIG. 11A. Therefore, even if the firmware ofthe processing section makes the second enable signals FCOMPENB, FSEENB1and FSEENB2 active before the VBUS voltage rises as indicated by A1,since these signals are masked by the VBUS detection signal VBDET, theenable signals COMPENB, SEENB1, and SEENB2 do not become active.Therefore, a problem in which unnecessary electric power is consumed bythe receiver circuit 30 before the USB cable is connected can beprevented.

The single end receivers 34 and 36 are enabled before the timing T1shown in FIG. 11A (at timing between the timing at which the VBUSdetection signal VBDET becomes active and the timing T1), for example.Power consumption can be minimized by enabling the differential receiver32 before the timing T6 shown in FIG. 11B (timing between the timings T1and T6), whereby an optimum power management can be implemented.

-   9. Electronic Instrument

FIG. 12 shows an electronic instrument according to one embodiment ofthe present invention. An electronic instrument 300 includes a datatransfer control device 310 described in this embodiment, an applicationlayer device 320 formed by ASIC or the like, a CPU 330, a ROM 340, a RAM350, a display section 360, and an operation section 370. The electronicinstrument 300 may have a configuration in which some of thesefunctional blocks are omitted.

The application layer device 320 is a device which implements anapplication engine of a portable telephone, a device which controls adrive of an information storage medium (hard disk or optical disk), adevice which controls a printer, a device including an MPEG encoder andan MPEG decoder, or the like. The processing section 330 (CPU) controlsthe data transfer control device 310 and the entire electronicinstrument. The ROM 340 stores a control program and various types ofdata. The RAM 350 functions as a work area and a data storage area forthe processing section 330 and the data transfer control device 310. Thedisplay section 360 displays various types of information to the user.The operation section 370 allows the user to operate the electronicinstrument.

In FIG. 12, a DMA bus and a CPU bus are separated. However, these busesmay be one common bus. A processing section which controls the datatransfer control device 310 and a processing section which controls theelectronic instrument may be provided independently. As examples ofelectronic instruments to which this embodiment can be applied, portabletelephones, optical disk (CD-ROM and DVD) drives, magneto-optical (MO)disk drives, hard disk drives, TVs, TV tuners, VTRs, video cameras,audio devices, projectors, personal computers, electronic notebooks,PDAs, word processors, and the like can be given.

Although only some embodiments of the present invention have beendescribed in detail above, those skilled in the art will readilyappreciate that many modifications are possible in the embodimentswithout departing from the novel teachings and advantages of thisinvention. Accordingly, all such modifications are intended to beincluded within the scope of this invention.

Any term (such as USB, DP, DM, VSS, VDD, P-type, and N-type) cited witha different term having broader or the same meaning (such as a giveninterface standard, a first signal, a second signal, a first powersupply, a second power supply, a first conductivity type, and a secondconductivity type) at least once in this specification and drawings canbe replaced by the different term in any place in this specification anddrawings.

The configurations of the data transfer control device, the physicallayer circuit, the VBUS detection circuit, the reception controlcircuit, and the like implemented by the present invention are notlimited to the configurations shown in FIGS. 1 to 3, 10, etc. It ispossible to make various modifications. The configurations of thedifferential receiver and the single end receiver are not limited to theconfigurations described with reference to FIGS. 6 to 9. It is possibleto make various modifications.

1. A physical layer circuit for data transfer using a Universal SerialBus (USB), the physical layer circuit comprising: a VBUS detectioncircuit which monitors a voltage of a VBUS line of USB, and makes a VBUSdetection signal active when the voltage of the VBUS line has exceeded apredetermined voltage; a receiver circuit which receives first andsecond signals which are differential signals and performs receptionprocessing using the first and second signals; and a reception controlcircuit which outputs a first enable signal to the receiver circuit, thereception control circuit making the first enable signal inactive anddisables the receiver circuit when the VBUS detection signal isinactive, the reception control circuit receiving a second enable signalset by a processing section, the reception control circuit disabling thereceiver circuit when the second enable signal is active but the VBUSdetection signal is inactive, and the reception control circuit makingthe first enable signal active and enables the receiver circuit when thesecond enable signal and the VBUS detection signal are active.
 2. Thephysical layer circuit as defined in claim 1, wherein: the VBUSdetection circuit includes a first resistor provided between the VBUSline and a detection node and a second resistor provided between thedetection node and a node of a first power supply; and the VBUSdetection circuit makes the VBUS detection signal active when a voltageof the detection node has exceeded a predetermined detection voltage. 3.The physical layer circuit as defined in claim 2, whereinVB×RV1/(RV1+RV2)<VR is satisfied, where RV1 and RV2 representresistances of the first and second resistors, VB represents a voltagesupplied to the VBUS line, and VR represents a rated voltage of the VBUSdetection circuit.
 4. The physical layer circuit as defined in claim 2,wherein RV1+RV2>VB/IS is satisfied, where RV1 and RV2 representresistances of the first and second resistors, VB represents a voltagesupplied to the VBUS line, and IS represents an allowable value ofcurrent flowing from the VBUS line to the physical layer circuit insuspend mode.
 5. The physical layer circuit as defined in claim 1,wherein: the receiver circuit includes a differential receiver havingfirst and second differential inputs to which the first and secondsignals are respectively input; and a current source transistor of anoperational amplifier circuit in the differential receiver is turned OFFwhen the first enable signal is inactive.
 6. The physical layer circuitas defined in claim 2, wherein: the receiver circuit includes adifferential receiver having first and second differential inputs towhich the first and second signals are respectively input; and a currentsource transistor of an operational amplifier circuit in thedifferential receiver is turned OFF when the first enable signal isinactive.
 7. The physical layer circuit as defined in claim 5, furthercomprising: a reference voltage generation circuit which outputs areference voltage to the current source transistor, wherein an outputnode of the reference voltage generation circuit is set to a powersupply voltage and a current flowing through the reference voltagegeneration circuit is terminated, when the first enable signal isinactive.
 8. The physical layer circuit as defined in claim 6, furthercomprising: a reference voltage generation circuit which outputs areference voltage to the current source transistor, wherein an outputnode of the reference voltage generation circuit is set to a powersupply voltage and a current flowing through the reference voltagegeneration circuit is terminated, when the first enable signal isinactive.
 9. A physical layer circuit for data transfer using aUniversal Serial Bus (USB), the physical layer circuit comprising: aVBUS detection circuit which monitors a voltage of a VBUS line of USB,and makes a VBUS detection signal active when the voltage of the VBUSline has exceeded a predetermined voltage; a receiver circuit whichreceives first and second signals which are differential signals andperforms reception processing using the first and second signals; areception control circuit which outputs a first enable signal to thereceiver circuit, wherein the reception control circuit makes the firstenable signal inactive and disables the receiver circuit when the VBUSdetection signal is inactive; and a reference voltage generation circuitwhich outputs a reference voltage to a current source transistor whichis included in an operational amplifier circuit of a differentialreceiver of the receiver circuit, wherein the reference voltagegeneration circuit includes: first and second transistors which are of afirst conductivity type and form a current mirror circuit; thirdtransistor which is of a second conductivity type, connected in serieswith the first transistor, and turned ON when the first enable signal isactive; fourth transistor which is of the second conductivity type,connected in series with the second transistor, and has a gate and adrain connected to an output node of the reference voltage generationcircuit; and fifth transistor which is of the second conductivity typeand provided between the output node and a node of a first power supply,wherein the third transistor is turned OFF and the fifth transistor isturned ON when the first enable signal is inactive.
 10. A physical layercircuit for data transfer using a Universal Serial Bus (USB), thephysical layer circuit comprising: a VBUS detection circuit whichmonitors a voltage of a VBUS line of USB, and makes a VBUS detectionsignal active when the voltage of the VBUS line has exceeded apredetermined voltage; a receiver circuit which receives first andsecond signal which are differential signals and performs receptionprocessing using the first and second signals; wherein the VBUSdetection circuit includes a first resistor provided between the VBUSline and a detection node and a second resistor provided between thedetection node and a first power supply; and a reception control circuitwhich outputs a first enable signal to the receiver circuit, wherein thereception control circuit makes the first enable signal inactive anddisables the receiver circuit when the VBUS detection signal isinactive; and a reference voltage generation circuit which outputs areference voltage to a current source transistor which is included in anoperational amplifier circuit of a differential receiver of the receivercircuit, wherein the reference voltage generation circuit includes:first and second transistors which are of a first conductivity type andform a current mirror circuit; third transistor which is of a secondconductivity type, connected in series with the first transistor, andturned ON when the first enable signal is active; fourth transistorwhich is of the second conductivity type, connected in series with thesecond transistor, and has a gate and a drain connected to an outputnode of the reference voltage generation circuit; and fifth transistorwhich is of the second conductivity type and provided between the outputnode and a node of a first power supply; and wherein the thirdtransistor is turned OFF and the fifth transistor is turned ON when thefirst enable signal is inactive.
 11. The physical layer circuit asdefined in claim 1, wherein: the receiver circuit includes a firstsingle end receiver having an input to which the first signal is input,and a second single end receiver having an input to which the secondsignal is input; wherein each of the first and second single endreceivers includes a first inverter circuit to which the first or secondsignal is input, and a second inverter circuit having an input to whichan output node of the first inverter circuit is connected; and whereinthe output node of the first inverter circuit and an output node of thesecond inverter circuit are set to a first power supply voltage and asecond power supply voltage when the first enable signal is inactive.12. The physical layer circuit as defined in claim 2, wherein: thereceiver circuit includes a first single end receiver having an input towhich the first signal is input, and a second single end receiver havingan input to which the second signal is input; wherein each of the firstand second single end receivers includes a first inverter circuit towhich the first or second signal is input, and a second inverter circuithaving an input to which an output node of the first inverter circuit isconnected; and wherein the output node of the first inverter circuit andan output node of the second inverter circuit are set to a first powersupply voltage and second power supply voltage when the first enablesignal is inactive.
 13. A physical layer circuit for data transfer usinga Universal Serial Bus (USB), the physical layer circuit comprising: aVBUS detection circuit which monitors a voltage of a VBUS line of USB,and makes a VBUS detection signal active when the voltage of the VBUSline has exceeded a predetermined voltage; a receiver circuit whichreceives first and second signals which are differential signals andperforms reception processing using the first and second signals; areception control circuit which outputs a first enable signal to thereceiver circuit, wherein the reception control circuit makes the firstenable signal inactive and disables the receiver circuit when the VBUSdetection signal is inactive; a first inverter circuit to which thefirst or second signal is input and being included in each of first andsecond single end receivers of the receiver circuit; and a secondinverter circuit having an input to which an output node of the firstinverter circuit is connected and being included in each of the firstand second single end receivers of the receiver circuit wherein thefirst inverter circuit includes: a first transistor which is of a firstconductivity type, provided between a node of a second power supply anda first intermediate node, and set to an ON state; a second transistorwhich is of the first conductivity type, provided between the firstintermediate node and the output node of the first inverter circuit, andhas a gate to which the first or second signal is input; a thirdtransistor which is of a second conductivity type, provided between theoutput node and a second intermediate node, and has a gate to which thefirst or second signal is input; a fourth transistor which is of thesecond conductivity type, provided between the second intermediate nodeand a node of a first power supply, and set to an ON state; a fifthtransistor which is of the first conductivity type, provided between thenode of the second power supply and the first intermediate node, and hasa gate to which a feedback signal from the second inverter circuit isinput; a sixth transistor which is of the first conductivity type andprovided between the first intermediate node and the output node; and aseventh transistor which is of the second conductivity type, providedbetween the second intermediate node and the node of the first powersupply, and has a gate to which the feedback signal is input, whereinthe sixth transistor is turned ON when the first enable signal isinactive.
 14. A physical layer circuit for data transfer using aUniversal Serial Bus (USB), the physical layer circuit comprising: aVBUS detection circuit which monitors a voltage of a VBUS line of USB,and makes a VBUS detection signal active when the voltage of the VBUSline has exceeded a predetermined voltage; a receiver circuit whichreceives first and second signal which are differential signals andperforms reception processing using the first and second signals;wherein the VBUS detection circuit includes a first resistor providedbetween the VBUS line and a detection node and a second resistorprovided between the detection node and a first power supply; areception control circuit which outputs a first enable signal to thereceiver circuit, wherein the reception control circuit makes the firstenable signal inactive and disables the receiver circuit when the VBUSdetection signal is inactive; a first inverter circuit to which thefirst or second signal is input and being included in each of first andsecond single end receivers of the receiver circuit; and a secondinverter circuit having an input to which an output node of the firstinverter circuit is connected and being included in each of the firstand second single end receivers of the receiver circuit wherein thefirst inverter circuit includes: a first transistor which is of a firstconductivity type, provided between a node of a second power supply anda first intermediate node, and set to an ON state; a second transistorwhich is of the first conductivity type, provided between the firstintermediate node and the output node of the first inverter circuit, andhas a gate to which the first or second signal is input; a thirdtransistor which is of a second conductivity type, provided between theoutput node and a second intermediate node, and has a gate to which thefirst or second signal is input; a fourth transistor which is of thesecond conductivity type, provided between the second intermediate nodeand a node of a first power supply, and set to an ON state; a fifthtransistor which is of the first conductivity type, provided between thenode of the second power supply and the first intermediate node, and hasa gate to which a feedback signal from the second inverter circuit isinput; a sixth transistor which is of the first conductivity type andprovided between the first intermediate node and the output node; and aseventh transistor which is of the second conductivity type, providedbetween the second intermediate node and the node of the first powersupply, and has a gate to which the feedback signal is input, whereinthe sixth transistor is turned ON when the first enable signal isinactive.
 15. The physical layer circuit as defined in claim 1, whereinthe receiver circuit is a USB full speed receiver circuit.
 16. A datatransfer control device, comprising: the physical layer circuit asdefined in claim 1; and a transfer controller which controls datatransfer using USB.
 17. An electronic instrument, comprising: the datatransfer control device as defined in claim 16; and a processing sectionwhich controls the data transfer control device.
 18. A physical layercircuit for data transfer using a Universal Serial Bus (USB), thephysical layer circuit comprising: a VBUS detection circuit whichmonitors a voltage of a VBUS line of USB, and makes a VBUS detectionsignal active when the voltage of the VBUS line has exceeded apredetermined voltage; a receiver circuit which receives first andsecond signals which are differential signals and performs receptionprocessing using the first and second signals; and a reception controlcircuit which outputs a first enable signal to the receiver circuit,wherein the reception control circuit makes the first enable signalinactive and disables the receiver circuit when the VBUS detectionsignal is inactive; the receiver circuit includes a differentialreceiver having first and second differential inputs to which the firstand second signals are respectively input; and a current sourcetransistor of an operational amplifier circuit in the differentialreceiver turned off when the first enable signal is inactive; areference voltage generation circuit which outputs a reference voltageto the current source transistor, wherein an output node of thereference voltage generation circuit is set to a power supply voltage ina current flowing through the reference voltage generation circuit isterminated, when the first enable circuit is inactive; wherein thereference voltage generation circuit includes: first and secondtransistors which are of a first conductivity type and form a currentmirror circuit; third transistor which is of a second conductivity type,connected in series with the first transistor, and turned on when thefirst enable signal is active; fourth transistor which is of the secondconductivity type, connected in series with the second transistor, andhas a gate and a drain connected to the output node of the referencevoltage generation circuit; and fifth transistor which is of the secondconductivity type and provided between the output node and a node of afirst power supply; and wherein the third transistor is turned off andthe fifth transistor is turned on when the first enable signal isinactive.
 19. A physical layer circuit for data transfer using aUniversal Serial Bus (USB), the physical layer circuit comprising: aVBUS detection circuit which monitors a voltage of a VBUS line of USB,and makes a VBUS detection signal active when the voltage of the VBUSline has exceeded a predetermined voltage; and a receiver circuit whichreceives first and second signals which are differential signals andperforms reception processing using the first and second signals,wherein the VBUS detection circuit includes a first resistor providedbetween the VBUS line and a detection node and a second resistorprovided between the detection node and a node of a first power supply;the receiver circuit includes a differential receiver having first andsecond differential inputs to which the first and second signals arerespectively input; and a current source transistor of an operationalamplifier circuit in the differential receiver is turned off when thefirst enable signal is inactive; a reference voltage generation circuitwhich outputs a reference voltage to the current source transistor,wherein in output node of the reference voltage generation circuit isset to a power supply voltage and a current flowing through thereference voltage generation circuit is terminated, when the firstenable signal is inactive; wherein the reference voltage generationcircuit includes: first and second transistors which are of a firstconductivity type and form a current mirror circuit; third transistorwhich is of a second conductivity type, connected in series with thefirst transistor, and turned on when the first enable signal is active;fourth transistor which is of the second conductivity type, connected inseries with the second transistor, and has a gate and a drain connectedto the output node of the reference voltage generation circuit; andfifth transistor which is of the second conductivity type and providedbetween the output node and a node of a first power supply; and whereinthe third transistor is turned off and the fifth transistor is turned onwhen the first enable signal is inactive.
 20. A physical layer circuitfor data transfer using a Universal Serial Bus (USB), the physical layercircuit comprising: a VBUS detection circuit which monitors a voltage ofa VBUS line of USB, and makes a VBUS detection signal active when thevoltage of the VBUS line has exceeded a predetermined voltage; areceiver circuit which receives first and second signals which aredifferential signals and performs reception processing using the firstand second signals; and a reception control circuit which outputs afirst enable signal to the receiver circuit, wherein the receptioncontrol circuit makes the first enable signal inactive and disables thereceiver circuit when the VBUS detection signal is inactive; thereceiver circuit includes a first single end receiver having an input towhich the first signal is input, and a second single and receiver havingan input into which the second signal is input; wherein in each of thefirst and second single and receivers includes a first inverter circuitto which the first or second signal is input and a second invertercircuit having an input to which an output node of the first invertercircuit is connected; wherein in the output node of the first invertercircuit and an output node of the second inverter circuit are set to afirst power supply voltage and a second power supply voltage when thefirst enable signal is inactive; wherein the first inverter circuitincludes: a first transistor which is of a first conductivity type,provided between a node of a second power supply and a firstintermediate node, and set to an on state; a second transistor which isof the first conductivity type, provided between the first intermediatenode and the output node of the first inverter circuit, and has a gateto which the first or second signal is input; a third transistor whichis of a second conductivity type, provided between the output node and asecond intermediate node, and has a gate to which the first or secondsignal is input; a fourth transistor which is of the second conductivitytype, provided between the second intermediate node and a node of afirst power supply, and set to an on state; a fifth transistor which isof the first conductivity type, provided between the node of the secondpower supply and the first intermediate node, and has a gate to which afeedback signal from the second inverter circuit in input; a sixthtransistor which is of the first conductivity type, provided between thefirst intermediate node and the output node; and a seventh transistorwhich is of the second conductivity type, provided between the secondintermediate node and the node of the first power supply, and has a gateto which the feedback signal is input; and wherein the sixth transistoris turned on when the first enable signal is inactive.
 21. A physicallayer circuit for data transfer using a Universal Serial Bus (USB), thephysical layer circuit comprising: a VBUS detection circuit whichmonitors a voltage of a VBUS line of USB, and makes a VBUS detectionsignal active when the voltage of the VBUS line has exceeded apredetermined voltage; and a receiver circuit which receives first andsecond signals which are differential signals and performs receptionprocessing using the first and second signals, wherein the VBUSdetection circuit includes a first resistor provided between the VBUSline and a detection node and a second resistor provided between thedetection node and a node of a first power supply; wherein the VBUSdetection circuit makes the VBUS detection signal active when a voltageof the detection node has exceeded a predetermined detection voltage;the receiver circuit includes a first single end receiver having inputto which the first signal is input, and a second single end receiverhaving input to which the second signal in input; wherein each of thefirst and second single end receivers includes a first inverter circuitto which the first or second signal is input, and a second invertercircuit having an input to which an output node of the first invertercircuit is connected; wherein the output node of the first invertercircuit and an output node of the second inverter circuit are set to afirst power supply voltage and a second power supply voltage when thefirst enable signal in inactive; wherein the first inverter circuitincludes: a first transistor which is of a first conductivity type,provided between a node of a second power supply and a firstintermediate node, and set to an ON state; a second transistor which isof the first conductivity type, provided between the first intermediatenode and the output node of the first inverter circuit, and has a gateto which the first or second signal is input; a third transistor whichis of a second conductivity type, provided between the output node and asecond intermediate node, and has a gate to which the first or secondsignal is input; a fourth transistor which is of the second conductivitytype, provided between the second intermediate node and a node of afirst power supply, and set to an ON state; a fifth transistor which isof the first conductivity type, provided between the node of the secondpower supply and the first intermediate node, and has a gate to which afeedback signal from the second inverter circuit is input; a sixthtransistor which is of the first conductivity type and provided betweenthe first intermediate node and the output node; and a seventhtransistor which is of the second conductivity type, provided betweenthe second intermediate node and the node of the first power supply, andhas a gate to which the feedback signal is input; and wherein the sixthtransistor is turned ON when the first enable signal is inactive.